With the appearance of super-fast microprocessors and multiprocessor systems, the chief bottleneck in computers now centers on I/O. Parallel shared-bus architectures such as PCI are no longer up to the task - at high speeds they suffer from noise and latency problems. Boosting bandwidth beyond 1 Gbps demands a point-to-point interconnect scheme, not a shared bus, and therefore a switch-based architecture.
In such an architecture, backplane signals (in the form of low-voltage differential signaling) are usually routed through a central switch chip instead of spread across a parallel bus, and find their way to the correct boards or chassis via the lanes of the switching fabric. Multiple processors then operate without signal collisions.
HyperTransport, InfiniBand, PCI Express, RapidIO, and StarFabric lead the crop of switch-based architectures now rising to take the place of PCI and ISA busses. Of these, PCI Express (formerly known as 3GIO) has the most going for it. This is partly because of its backward compatibility with software written for PCI, but mainly because mighty Intel is putting its full 800 pounds of muscle behind it. This fact has not been lost on PLX Technology (Sunnyvale, CA - 408-774-9060, www.plxtech.com), which recently announced a set of PCI Express-compliant interconnection devices based on its new PLX BulletTrain on-chip architecture. More of PLX's PCI Express products will appear in early 2004.
PLX's BulletTrain is a non-blocking, high-performance on-chip switching mesh that allows rapid reuse of protocol-specific intellectual property (IP), providing a modular building block that can be used by future products. This IP reuse reduces new product engineering effort to system integration and verification, greatly speeding time to market.
The basic PCI Express configuration is a single bidirectional high-speed serial path. PCI Express needs no extraneous sideband signals, and even the clocking signal is incorporated into the basic link. Bandwidth is scaled up from 2.5 Gbps to 128 Gbps by duplicating the serial link paths on the backplane in multiples of 2, 4, 8, 12, 16, and 32.
Larry Chisvin, VP of Marketing for PLX, says: "Since PCI Express has fewer signal paths, each chip needs fewer pins. Chip components may be reduced in size from 0.25 to 0.13 microns, but if it needs the same number of pins, the die to make the chip has to be just as big as before, and the chip as expensive. Look at PCI-X, for example, where a chip for a high-bandwidth system must have a hundred or so pins. With PCI Express, the basic configuration is just four pins, and an eight-gigabit bandwidth system just 16."
Aside from the cost advantage, PCI Express systems boast features that are unavailable in standard PCI, says Chisvin. "The core or base specification offers QoS, data integrity, and hot-plug support. The Advanced Switching, or AS specification, introduces a network layer that builds on the transaction layer of the base architecture. It adds features especially important to telecom, such as a flat global addressing scheme, multi-host failover, a true peer-to-peer transfer scheme among two or more nodes within the fabric, and the ability to build systems that mix core and AS endpoints in any combination. This allows legacy PCI-based silicon devices to be used in a PCI Express environment."
PCI Express will also find a home in the new PICMG 3.0 AdvancedTCA (ATCA) form factor. This defines computers with larger, more powerful, and better-spaced boards than CompactPCI or VMEbus. PLX, in fact, is designated "editor" of the PICMG 3.4 Subcommittee that is actually putting the ATCA specification into writing.
"PLX makes Rapid Development Kits," says Chi, "that contain our example boards. For PCI Express we're going to be using the ATCA as our RDK platform, in the same way that we used CompactPCI for our previous RDKs. It makes sense to us to put PCI Express on ATCA hardware, because we think that early adopters looking for high performance standardized equipment will want to take advantage of ATCA's feature set."
